Method for manufacturing thin film transistor, and thin film transistor thereof

ABSTRACT

The present invention relates to the field of liquid crystal display, and provides a method for manufacturing a TFT and the TFT thereof. The TFT comprises: a substrate; a gate electrode with a three-dimensional structure formed on the substrate; a gate insulating layer for covering the gate electrode; a semiconductor layer formed on the gate insulating layer; a buffer layer formed on the semiconductor layer; and source and drain electrodes formed on the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure. According to the present invention, it is able to reduce the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

CROSS REFERENCE

The present application claims a priority of the Chinese patent application No. 201210460335.2 filed on Nov. 15, 2012, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates to the field of liquid crystal display, in particular to a method for manufacturing a thin film transistor and the thin film transistor thereof.

BACKGROUND

In the field of display, flat-panel displays with high PPI (Pixels per inch) values have become a key competition for manufacturers. However, when the panel has a high PPI value, a number of issues in, for example, power consumption and light transmission will occur. As a result, it has become a technical problem to increase a saturation current and ensure a certain charging rate by increasing the channel width in the case of a reduced opaque area for a TFT (Thin Film Transistor) array substrate.

For the existing TFT array substrate, its channel and gate electrode layer are of a flat structure as a film, so it is impossible to fully and reasonably utilize a spatial volume to increase the saturation current.

SUMMARY

An object of the present invention is to provide a method for manufacturing a TFT and the TFT thereof, so as to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

In one aspect, the present invention provides a method for manufacturing a TFT, comprising the steps of :

providing a substrate;

forming a gate electrode with a three-dimensional structure on the substrate;

forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed;

forming a semiconductor layer on the substrate on which the gate insulating layer is formed;

forming a buffer layer on the substrate on which the semiconductor layer is formed; and

forming a metal layer on the substrate on which the buffer layer is formed, and treating the metal layer by a patterning process to form source and drain electrodes,

wherein the semiconductor layer of the TFT is of a three-dimensional structure.

Preferably, the three-dimensional structure of the gate electrode is a cuboid or cube.

The three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.

A portion of the semiconductor layer between the source and drain electrodes forms a channel. A length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode).

The step of forming a gate electrode with a three-dimensional structure on the substrate comprises:

depositing a first metal layer on the substrate; and

treating the first metal layer by a patterning process to form the gate electrode with a three-dimensional structure.

The first metal layer may be made of ITO, or a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu or an alloy thereof.

The step of forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed comprises:

depositing an insulating material layer on the substrate on which the gate electrode with a cuboid structure is formed; and

treating the insulating material layer by a patterning process to form the gate insulating layer on a top face and two side faces of the gate electrode.

The step of forming a semiconductor layer on the substrate on which the gate insulating layer comprises:

depositing a semiconductor material layer on the substrate on which the gate insulating layer is formed; and

treating the semiconductor material layer by a patterning process to form the semiconductor layer on the gate insulating layer.

The step of forming a buffer layer on the substrate on which the semiconductor layer is formed comprises:

depositing an N+ amorphous silicon material layer on the substrate on which the semiconductor layer is formed; and

treating the N+ amorphous silicon material layer by a patterning process to form the buffer layer on the semiconductor layer.

The step of forming a metal layer on the substrate on which the buffer layer is formed and treating the metal layer by a patterning process to form source and drain electrodes comprises:

depositing a second metal layer on the substrate on which the buffer layer is formed; and

treating the second metal layer by a patterning process to form the source and drain electrodes on the buffer layer.

The second metal layer may be made of a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu or an alloy thereof.

In another aspect, the present invention further provides a TFT, comprising:

a substrate;

a gate electrode with a three-dimensional structure formed on the substrate;

a gate insulating layer for covering the gate electrode;

a semiconductor layer formed on the gate insulating layer;

a buffer layer formed on the semiconductor layer; and

source and drain electrodes formed on the buffer layer,

wherein the semiconductor layer of the TFT is of a three-dimensional structure.

Preferably, the three-dimensional structure of the gate electrode is a cuboid or cube.

The three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.

A portion of the semiconductor layer between the source and drain electrodes forms a channel. A length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode).

The channel of the TFT at least includes three electronic gates.

The above technical solutions of the present invention have the following beneficial effect.

According to solutions of the present invention, the number of the electronic gates will be increased due to the use of a TFT with a three-dimensional structure, that is, in the case of an identical gate voltage and an identical area occupied by the TFT, the TFT of the present invention has a saturation current larger than that of a traditional flat TFT. As a result, it is able to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing the structure of a TFT according to embodiments of the present invention; and

FIGS. 2-10 are schematic views showing a method for manufacturing a TFT according to embodiments of the present invention.

DETAILED DESCRIPTION Embodiment 1

As shown in FIGS. 2-10, the embodiment of the present invention provides a method for manufacturing a TFT, comprising:

Step 1: providing a substrate 11;

Step 2: forming a gate electrode with a three-dimensional structure on the substrate 11;

Step 3: forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed;

Step 4: forming a semiconductor layer on the substrate on which the gate insulating layer is formed;

Step 5: forming a buffer layer on the substrate on which the semiconductor layer is formed; and

Step 6: forming a metal layer on the substrate on which the buffer layer is formed, and treating the metal layer by a patterning process to form source and drain electrodes, wherein the semiconductor layer of the TFT is of a three-dimensional structure.

According to the embodiment of the present invention, the number of corresponding electronic gates are increased by forming a TFT with a three-dimensional structure on the substrate, that is, the TFT of the present invention has a saturation current larger than that of a traditional flat TFT in the case of an identical gate voltage and an identical area occupied by the TFT. As a result, it is able to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

As shown in FIGS. 2 and 3, Step 2 comprises:

Step 21: depositing a first metal layer 1′ on the substrate; and

Step 22: treating the first metal layer 1′ by a patterning process to form a gate electrode 1 with a three-dimensional structure, wherein the three-dimensional structure is a cuboid.

The first metal layer 1′ may be made of ITO, or a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.

An existing gate electrode is of a film structure with a very small thickness, while the gate electrode 1 of the present invention is of a three-dimensional structure with a thickness larger than a film. Preferably, the gate electrode 1 has a shape of cuboid. Other structures may be further provided on the basis of the gate electrode 1 having the shape of cuboid so that the entire TFT has a cuboid structure. It should be noted that, cuboid is merely a preferred shape for the TFT so as to facilitate the production and machining, and the TFT may also be a cube or any other shapes with a cross section of trapezoid or arch, as if it has a saturation current larger than a traditional flat TFT with a flat structure as a film in the case of an identical gate voltage and an identical area occupied by the TFT.

As shown in FIGS. 4 and 5, Step 3 comprises:

Step 31: depositing an insulating material layer 2′ on the substrate 11 on which the gate electrode 1 with a cuboid structure is formed (as shown in FIG. 4); and

Step 32: treating the insulating material layer 2′ by a patterning process to form the gate insulating layer 2 on a top face and two side faces of the gate electrode 1 (as shown in FIG. 5), wherein the gate insulating layer 2 may be made of oxides, nitrides or nitrogen oxides, such as SiNx.

As shown in FIGS. 6 and 7, Step 4 comprises:

Step 41: depositing a conductive material layer 3′ on the substrate 11 on which the gate insulating layer 2 is formed (as shown in FIG. 6); and

Step 42: treating the conductive material layer 3′ by a patterning process to form the semiconductor layer 3 on the gate insulating layer 2 (as shown in FIG. 7), wherein the three-dimensional structure of the semiconductor layer 3 is an inverted-U slot structure covering the gate electrode 1 (here, the structure of the semiconductor layer 3 is not limited, as if it covers the gate electrode and has the structure corresponding to that of the gate electrode), and the semiconductor layer 3 may be made of a-Si.

As shown in FIGS. 8 and 9, Step 5 comprises:

Step 51: depositing an N+ amorphous silicon material layer 4′ on the substrate 11 on which the semiconductor layer 3 is formed (as shown in FIG. 8); and

Step 52: treating the N+ amorphous silicon material layer 4′ (such as N+ a-Si) by a patterning process to form the buffer layer 4 on the semiconductor layer 3 (as shown in FIG. 9), wherein the buffer layer 4 may be a doped or a non-doped semiconductor layer.

As shown in FIG. 10, Step 6 comprises:

Step 61: depositing a second metal layer on the substrate 11 on which the buffer layer 4 is formed; and

Step 62: treating the second metal layer by a patterning process to finally form the source and drain electrodes 5 on the buffer layer 4 (as shown in FIG. 10), wherein the second metal layer may be made of a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.

FIG. 1 is a three-dimensional view showing the structure of the TFT with a three-dimensional structure finally obtained through the above-mentioned steps.

As show in FIG. 7, the three-dimensional structure of the semiconductor layer 3 may be an inverted-U slot structure covering the gate electrode, Due to this structure, the semiconductor layer 3 has three planes. A conductive channel will be formed in these planes during the operation of the TFT, so these planes constitute conductive gates, i.e., three electronic gates.

A portion of the semiconductor layer 3 between the source and drain electrodes forms a channel. A length of the channel is the distance between the source and drain electrodes. A width W of the channel≧(W1+W2+W3). W1 and W3 each represents a height of the gate electrode, and W2 represents a width of the gate electrode. As compared to the channel (with a width such as W2) for an existing flat structure, W is obviously greater than W2. Hence, according to the TFT of the present invention with a three-dimensional structure, the effective channel width is increased remarkably, so that the number of the electronic gates is increased correspondingly, e.g., at least three electronic gates. The TFT of the present invention has a saturation current greater than that of a traditional flat TFT in the case of an identical gate voltage and an identical area occupied by the TFT. As a result, it is able to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

According to the equation

${I_{saturation} = {\frac{W}{L} \cdot K \cdot \left( {V_{GS} - V_{TH}} \right)^{2}}},$

it can be seen that the saturation current will increase along with the channel width. In the equation, W represents a channel width, V_(GS) represents a voltage of the gate electrode 1 relative to the semiconductor layer 3, V_(TH) represents a minimum voltage desired for the induction of a carrier, K represents a Boltzmann constant, and L represents an effective channel length. As a result, it is able to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

Embodiment 2

As shown in FIGS. 1-10, the embodiment of the present invention provides a TFT, comprising: a substrate; a gate electrode 1 with a three-dimensional structure formed on the substrate; a gate insulating layer 2 for covering the gate electrode; a semiconductor layer 3 formed on the gate insulating layer 2; a buffer layer 4 formed on the semiconductor layer 3; and source and drain electrodes 5 formed on the buffer layer 4. A channel formed on the TFT is of a three-dimensional structure, e.g., a cuboid as shown in FIG. 1. The channel of the TFT at least comprises three electronic gates.

Other structures may be further provided on the basis of the gate electrode 1 with a cuboid structure so that the entire TFT also has a cuboid structure. It should be noted that, cuboid is merely a preferred shape for the TFT so as to facilitate the production and machining, and the TFT may also be a cube or any other shapes, as if it has a saturation current larger than a traditional flat TFT with a flat structure as a film in the case of an identical gate voltage and an identical area occupied by the TFT.

The TFT has a three-dimensional structure, so the number of the electronic gates may be increased, that is, the TFT has a saturation current greater than that of a traditional flat TFT in the case of an identical gate voltage and an identical area occupied by the TFT. According to the equation I_(saturation)=W/L·K·(V_(GS)−V_(TH))², it can be seen that the saturation current will increase along with the channel width. In the equation, W represents a channel width, V_(GS) represents a voltage of the gate electrode 1 relative to the semiconductor layer 3, V_(TH) represents a minimum voltage desired for the induction of a carrier, K represents a Boltzmann constant, and L represents an effective channel length. As a result, it is able to reduce, to some extent, the driving voltage, the power consumption of the driving circuit and the area occupied by the TFT, and to increase the light transmission rate.

The above are merely the preferred embodiments of the present invention. It should be noted that, a person skilled in the art may make improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be considered as the scope of the present invention. 

What is claimed is:
 1. A method for manufacturing a TFT (Thin Film Transistor), comprising the steps of: providing a substrate; forming a gate electrode with a three-dimensional structure on the substrate; forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed; forming a semiconductor layer on the substrate on which the gate insulating layer is formed; forming a buffer layer on the substrate on which the semiconductor layer is formed; and forming a metal layer on the substrate on which the buffer layer is formed, and treating the metal layer by a patterning process to form source and drain electrodes, wherein the semiconductor layer of the TFT is of a three-dimensional structure.
 2. The method according to claim 1, wherein the three-dimensional structure of the gate electrode is a cuboid or cube.
 3. The method according to claim 1, wherein the three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.
 4. The method according to claim 3, wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode).
 5. The method according to claim 2, wherein the step of forming a gate electrode with a three-dimensional structure on the substrate comprises: depositing a first metal layer on the substrate; and treating the first metal layer by a patterning process to form the gate electrode with a three-dimensional structure.
 6. The method according to claim 5, wherein the first metal layer can be made of ITO, or a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.
 7. The method according to claim 2, wherein the step of forming a gate insulating layer for covering the gate electrode on the substrate on which the gate electrode is formed comprises: depositing an insulating material layer on the substrate on which the gate electrode with a cuboid structure is formed; and treating the insulating material layer by a patterning process to form the gate insulating layer on a top face and two side faces of the gate electrode.
 8. The method according to claim 2, wherein the step of forming a semiconductor layer on the substrate on which the gate insulating layer comprises: depositing a semiconductor material layer on the substrate on which the gate insulating layer is formed; and treating the semiconductor material layer by a patterning process to form the semiconductor layer on the gate insulating layer.
 9. The method according to claim 2, wherein the step of forming a buffer layer on the substrate on which the semiconductor layer is formed comprises: depositing an N+ amorphous silicon material layer on the substrate on which the semiconductor layer is formed; and treating the N+ amorphous silicon material layer by a patterning process to form the buffer layer on the semiconductor layer.
 10. The method according to claim 2, wherein the step of forming a metal layer on the substrate on which the buffer layer is formed and treating the metal layer by a patterning process to form source and drain electrodes comprises: depositing a second metal layer on the substrate on which the buffer layer is formed; and treating the second metal layer by a patterning process to form the source and drain electrodes on the buffer layer.
 11. The method according to claim 10, wherein the second metal layer can be made of a metal selected from the group consisting of Cr, Mo, Al, Nd, Mo, W, Ti, Ta and Cu, or an alloy thereof.
 12. A TFT (Thin Film Transistor), comprising: a substrate; a gate electrode with a three-dimensional structure formed on the substrate; a gate insulating layer for covering the gate electrode; a semiconductor layer formed on the gate insulating layer; a buffer layer formed on the semiconductor layer; and source and drain electrodes formed on the buffer layer, wherein the semiconductor layer of the TFT is of a three-dimensional structure.
 13. The TFT according to claim 12, wherein the three-dimensional structure of the gate electrode is a cuboid or cube.
 14. The TFT according to claim 12, wherein the three-dimensional structure of the semiconductor layer is an inverted-U slot structure covering the gate electrode.
 15. The TFT according to claim 13, wherein a portion of the semiconductor layer between the source and drain electrodes forms a channel, a length of the channel is the distance between the source and drain electrodes, and a width of the channel≧(a width of the gate electrode+2*a height of the gate electrode).
 16. The TFT according to claim 15, wherein the channel of the TFT at least comprises three electronic gates. 